1. Field of the Invention
The present invention relates to a dynamic RAM having an improved dummy cell, and more particularly to a dynamic RAM comprising a full-sized dummy cell having equal capacitance value with a memory cell.
1. Description of the Prior Art
An array structure of a conventional dynamic RAM having a full-sized dummy cell is disclosed in, for example, the Patent Laying-Open Gazette No. 103191/1982. Since a full-sized dummy cell has the same structure as a memory cell, a read level of the dummy cell becomes an intermediate between a read level of the memory cell in the high level information stored condition and a read level of the same in the low level information stored condition even when there is unevenness in the RAM manufacturing process, and an operation margin is surely maintained. Therefore it is effective in a highly integrated dynamic RAM employing minute processing.
However, as a substrate potential is usually applied by an inner circuit, the dynamic RAM is susceptible to fluctuation of the substrate potential and there occurs a phenomenon such that the read voltage is lost due to the fluctuation thereof.
In addition, in a conventional full-sized dummy cell system, a sensing begins after a selected dummy word line is raised to a high level and then lowered to the low level, so that the access time in the dynamic RAM is increased.